MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 457

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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11).5.2.5 TRACE EXCEPTIONS. The MC68030 supports two modes of instruction
10-70
The coprocessor should return the null, CA=0 primitive with PF=0, while it
The protocol used to execute coprocessor cpSAVE, cpRESTORE, or condi-
tional category instructions does not change when a trace exception is pend-
struction. If the main processor is in the trace on change of flow mode and
an instruction places an address other than that of the next instruction in the
instruction concurrently with the execution of instructions by the main pro-
cessor. When a trace exception is pending, however, the main processor
must ensure that all processing associated with a cpGEN instruction has
been completed before it takes the trace exception. In this case, the main
processor continues to read the response CIR and to service the primitives
until it receives either a null, CA=0, PF= 1 primitive, or until exception pro-
cessing caused by a take post-instruction exception primitive has completed.
is completing the execution of the cpGEN instruction. The main processor
may service pending interrupts between reads of the response CIR if IA = 1
in these primitives (refer to Table 10-3). This protocol ensures that a trace
exception is not taken until all processing associated with a cpGEN instruction
tracing, discussed in 8.1.7 Trace Exception. In the trace on instruction exe-
exception after each instruction that alters the status register or places an
address other than the address of the next instruction in program counter.
ing in the main processor. The main processor performs a pending trace on
instruction execution exception after completing the execution of that in-
program counter, the processor takes a trace exception after it executes the
instruction.
If a trace exception is not pending during a general category instruction, the
main processor terminates communication with the coprocessor after read-
ing any primitive with CA=0. Thus, the coprocessor can complete a cpGEN
has completed.
a general category instruction is initiated, a trace exception is taken for the
tion handler. A cpSAVE instruction executed during the trace on change of
flow exception handler could thus suspend the execution of a concurrently
cution mode, the MC68030 takes a trace exception after completing each
instruction. In the trace on change of flow mode, the MC68030 takes a trace
If T1 :T0=01 in the MC68030 status register (trace on change of flow) when
instruction only when the coprocessor issues a transfer status register and
scanPC primitive with DR = 1 during the execution of that instruction. In this
case, it is possible that the coprocessor is still executing the cpGEN instruction
concurrently when the main processor begins execution of the trace excep-
operating cpGEN instruction.
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