MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 319

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9-18
L ~
this replacement algorithm. ATC hit rates are application dependent, but hit
sponding page descriptor that contains the physical address. The 28-bit log-
V -
F C -
LOGICAL ADDRESS
entry that is no longer valid. When all entries in the ATC are valid, the ATC
selects a valid entry to be replaced, using a pseudo least recently used al-
gorithm. The ATC uses a validity bit and an internal history bit to implement
rates ranging from 98% to greater than 99% can be expected.
Each ATC entry consists of a logical address and information from a corre-
ical (or tag) portion of
If possible, when the ATC stores a new address translation, it replaces an
27
This 3-bit field contains the function code bits (FC0-FC2) corresponding to
the logical address in this entry.
This 24-bit field contains the most significant logical address bits for this
This bit indicates the validity of the entry. If V is set, this entry is valid. This
bit is set when the MC68030 loads an entry. A flush operation clears the
entry, All 24 bits of this field are used in the comparison of this entry to
an incoming logical address when the page
bit. Specifically, any of these operations clear the V bit of an entry:
page sizes, the appropriate number of least significant bits of this field are
ignored.
• A PMOVE instruction with the FD bit equal to
• A PFLUSHA instruction.
• A PFLUSH instruction that selects this entry.
• A PLOAD instruction for a logical address and FC that matches the tag
• The selection of this entry for replacement by the replacement algo-
VALID
FUNCTION CODE
26
for this entry. The instruction writes a new entry (with the V bit set)
for the specified logical address.
into the CRP, SRP, TC, TT0, or TT1 register.
rithm of the ATC.
FC
24
J
23
each
MC68030 USER'S MANUAL
entry consists of three fields:
LOGICAL ADDRESS
size
is 256 bytes. For larger
zero
that loads a value
MOTOROLA
0
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