MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 475

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

11-12
An example using a series of instructions that require Equation (11-1) to
Therefore, the general Equation (11-1) can be used for both.
Top are footnoted in 11.6 INSTRUCTION TIMING TABLES.
The actual instruction-cache-case execution time for a stream of instructions
can be computed using Equation (11-1) or the general Equation (11-2). Equa-
tion (11-1) is used unless the instruction-cache case, head, and tail of an
effective address are required.
calculate the instruction-cache-case execution time follows. The assumptions
address time for either instruction. Since both of the instructions use register
operands only, there is no need to add effective address calculation times.
The following computations use Equation (11-1):
from an appropriate table use the general Equation (11-2) to calculate the
actual CC time. The CCea, Hea, and Tea values must be extracted from the
appropriate effective address table (either fetch effective address, fetch im-
The instructions that require the instruction-cache case, head, and tail of an
effective address (CCea, Hea, and Tea) to be overlapped with CCop, Hop, and
referred to in 11.6 INSTRUCTION TIMING TABLES apply.
Referring to the timing table in 11.6.8 Arithmetic/Logical Instructions, the
head, tail, and instruction-cache-case (CC) times for ADD.L A1,D1 and SUBA.L
D1,A2 are found. There is no footnote directing the user to add an effective
Instructions that require the addition of an effective address calculation time
Execution Time = CC1 + [CC2- min(H2,T1)]
The underlined numbers show the typical pattern for the comparison
1.
2.
of head and tail in the following equation.
ADD.L A1,D1
SUBA.L D1,A2
= 2+ [4- rain(4,0)]
=2+I4-01
= 6 clocks
MC68030 USER'S MANUAL
2.
1.
ADD.L
SUBA.L
Instruction
NOTE
Head
A1,D1
D1,A2
2
4
Tail
0
0
MOTOROLA
CC
2
4