EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 111

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

Table 46. I
PS006614-1208
Code
40h
48h
38h
68h
78h
B0h
Note: R = Read bit. The lsb is set to 1.
Addr + R transmitted,
I
ACK received
Addr + R transmitted,
ACK not received
Arbitration lost
Arbitration lost, SLA+W
received, ACK
transmitted
Arbitration lost,
General call addr
received, ACK
transmitted
Arbitration lost, SLA+R
received, ACK
transmitted
2
C State
2
C Master Receive Status Codes
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit
Microprocessor Response
For a 7-bit address, clear IFLG,
ACK = 0
Or clear IFLG, ACK = 1
For a 10-bit address, write
extended address byte to
DATA, clear IFLG
For a 7-bit address: set STA,
clear IFLG
Or set STP, clear IFLG
Or set STA & STP, clear IFLG
For a 10-bit address: Write
extended address byte to
DATA, clear IFLG
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, clear ACK = 0
Or clear IFLG, set ACK = 1
Same as code 68h
Write byte to DATA, clear IFLG,
clear ACK = 0
Or write byte to DATA, clear
IFLG, set ACK = 1
Next I
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended
address byte
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Transmit extended
address byte
Return to the IDLE state
Transmit START when
bus is free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Same as code 68h
Transmit last byte, receive
ACK
Transmit data byte,
receive ACK
2
C Action
Product Specification
I2C Serial I/O Interface
101