EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 57

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

GPIO Control Registers
PS006614-1208
Edge-Triggered Interrupts
Port x Data Registers
forces the pin High. The CPU must be enabled to respond to interrupts for the interrupt
request signal to be acted upon.
When the port is configured for edge-triggered interrupts, the corresponding port pin is
tristated. If the pin receives the correct edge from an external device, the port pin generates
an interrupt request signal to the CPU. Any time a port pin is configured for edge-trig-
gered interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the edge-trig-
gered interrupt. The programmer must set the bit in the Port x Data register to 1 before
entering either single- or dual-edge-triggered interrupt mode for that port pin.
When configured for dual-edge-triggered interrupt mode (GPIO Mode 6), both a rising
and a falling edge on the pin cause an interrupt request to be sent to the CPU.
When configured for single-edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data register determines if a positive or negative edge causes an interrupt
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
in interrupt request for rising edges.
The 16 GPIO Control Registers operate in groups of four with a set for each Port (A, B, C,
and D). Each GPIO port features a Port Data register, Port Data Direction register, Port
Alternate register 1, and Port Alternate register 2.
When the port pins are configured for one of the output modes, the data written to the
Port x Data registers, listed in
In all modes, reading from the Port x Data registers always returns the current sampled
value of the corresponding pins. When the port pins are configured as edge-triggered
interrupt sources, writing a 1 to the corresponding bit in the Port x Data register clears the
interrupt signal that is sent to the CPU. When the port pins are configured for edge-select-
able interrupts or level-sensitive interrupts, the value written to the Port x Data register bit
selects the interrupt edge or interrupt level. For more information see
Table 13
on page 48, are driven on the corresponding pins.
General-Purpose Input/Output
Product Specification
Table 12
on page 43.
eZ80190
47