EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 112

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

Table 47. I
PS006614-1208
Code
50h
58h
38h
Note:
Slave Transmit
I
Data byte received,
ACK transmitted
Data byte received,
NACK transmitted
Arbitration lost in
NACK bit
2
C State
2
C Master Receive Status Codes For Data Bytes
address again, but with the READ bit. The status code is then
remains selected prior to the restart.
If a repeated START condition is received, the status code is
After each data byte is received, the IFLG is set and one of the status codes listed in
Table 47
When all bytes are received, a NACK is sent. Next, the microprocessor writes a 1 to the
STP bit in the I2Cx_CTL register. The I
STP bit, and returns to the IDLE state.
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver. The
I
after a START condition. The I
to 1, and sets the IFLG bit in the I2Cx_CTL register. The I2Cx_SR register contains the
status code
2
C enters SLAVE TRANSMIT mode when it receives its own slave address and a read bit
When the I
register), it transmits an ACK after the first address byte is received after a restart. An
interrupt is generated, IFLG is set; however, the status does not change. No second
address byte is sent by the master. The slave remains selected prior to the restart.
is contained in the I2Cx_SR register.
A8h
2
C contains a 10-bit slave address (signified by
.
Microprocessor Response
Read DATA, clear IFLG, clear
ACK = 0
Or read DATA, clear IFLG, set
ACK = 1
Read DATA, set STA, clear
IFLG
Or read DATA, set STP, clear
IFLG
Or read DATA, set STA & STP,
clear IFLG
Same as master transmit
2
C then transmits an I
2
C then transmits a STOP condition, clears the
Next I
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Same as master transmit
2
C Acknowledge bit (ACK) if it is set
2
C Action
10h
F0h
40h
Product Specification
–
instead of
or
F7h
I2C Serial I/O Interface
48h
in the I2Cx_SAR
. The slave
08h
.
102