EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 158

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

ZDI Interface
ZDI Clock and Data Conventions
PS006614-1208
PROCESSOR
TARGET
as the ZDI can download and upload data, with a maximum frequency of one-half the
CPU clock frequency.
ZDI supports a bidirectional serial protocol. The protocol defines any device that sends
data as the transmitter and any receiving device as the receiver. The device controlling the
transfer is the master and the device being controlled is the slave. The master always ini-
tiates the data transfers and provides the clock for both receive and transmit operations.
The ZDI block on the eZ80190 device is considered a slave in all data transfers.
Figure 27
tor allows you to connect directly to the ZPAK II emulator using a six-pin header.
The two pins used for communication with the ZDI block are the ZDI Clock pin (ZCL)
and the ZDI Data pin (ZDA). For general data communication, the data value on the ZDA
pin can change only when ZCL is Low (0). The only exception is the ZDI START bit,
which is indicated by a High-to-Low transition (falling edge) on the ZDA pin while ZCL
is High.
Data is shifted into and out of ZDI, with the msb (bit 7) of each byte being transferred first,
and the lsb (bit 0) transferred last. All information is passed between the master and the
slave in 8-bit (single-byte) units. Each byte is transferred with nine clock cycles: eight to
shift the data, and the ninth for internal operations.
Figure 27. Schematic For Building a Target Board ZPAK II Connector
displays the schematic for building a connector on a target board. This connec-
ZCL
ZDA
330K
6-Pin Target Connector
330K
2
4
6
5
3
1
Product Specification
(Target V
TV
Zilog Debug Interface
DD
DD
)
eZ80190
148