EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 167

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

PS006614-1208
Bit
Position
6
BRK_ADDR3
5
BRK_ADDR2
4
BRK_ADDR1
Value Description
0
1
0
1
0
1
The ZDI break, upon matching break address 3, is disabled.
The ZDI break, upon matching break address 3, is enabled.
ZDI asserts a break when the CPU address, ADDR[23:0],
matches the value in the ZDI Address Match 3 registers,
{ZDI_ADDR3_U, ZDI_ADDR3_H, ZDI_ADDR3_L}. Breaks can
only occur on an instruction boundary. If the address is not the
beginning of an instruction, then the break occurs at the end of
the current instruction. The break is implemented by setting the
BRK_NEXT bit to 1.The BRK_NEXT bit must be reset to 0 to
release the break.
The ZDI break, upon matching break address 2, is disabled.
The ZDI break, upon matching break address 2, is enabled.
ZDI asserts a break when the CPU address, ADDR[23:0],
matches the value in the ZDI Address Match 2 registers,
{ZDI_ADDR2_U, ZDI_ADDR2_H, ZDI_ADDR2_L}. Breaks can
only occur on an instruction boundary. If the address is not the
beginning of an instruction, then the break occurs at the end of
the current instruction. The break is implemented by setting the
BRK_NEXT bit to 1. The BRK_NEXT bit must be reset to 0 to
release the break.
The ZDI break, upon matching break address 1, is disabled.
The ZDI break, upon matching break address 1, is enabled.
ZDI asserts a break when the CPU address, ADDR[23:0],
matches the value in the ZDI Address Match 1 registers,
{ZDI_ADDR1_U, ZDI_ADDR1_H, ZDI_ADDR1_L}. If the
IGN_LOW_1 bit is set to 1, ZDI asserts a break with the upper
two bytes of the CPU address, ADDR[23:8], and matches the
value in the ZDI Address Match 1 High and Low Byte registers,
{ZDI_ADDR1_U, ZDI_ADDR1_LH}. The lower byte of the
address is ignored. Breaks can only occur on an instruction
boundary. If the address is not the beginning of an instruction,
then the break occurs at the end of the current instruction. The
break is implemented by setting the BRK_NEXT bit to 1. The
BRK_NEXT bit must be reset to 0 to release the break.
Product Specification
Zilog Debug Interface
eZ80190
157