EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 64

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

I/O Chip Select Precaution
Wait States
PS006614-1208
•
For all I/O operations, the upper byte of the address bus, ADDR[23:16], is forced to
The I/O Chip Selects do not compare the values stored in the CSx_LBR registers to what
is generally considered to be the High byte of the I/O address, or ADDR[15:8]. Instead,
the I/O Chip Selects compare the values stored in the CSx_LBR registers to a byte taken
from the middle of the I/O address, or ADDR[11:4].
For each of the four available Chip Selects, programmable WAIT states can be inserted to
provide external devices with additional clock cycles to complete their read and write
operations. The number of WAIT states for a particular Chip Select is controlled by the 3-
bit field CSx_wait (CSx_CTL[7:5]). The Chip Selects can be independently programmed
to provide 0 to 7 WAIT states. The WAIT states idle the CPU for the specified number of
system clock cycles. An example of WAIT state operation is displayed in
on page 55. In this example, a single WAIT state is added. It causes the instruction read
operation to use an additional clock cycle. WAIT is an internal signal used by the eZ80190
device. See
Depending upon the instruction, either RD or WR are activated (driven Low)
Figure 9
on page 55.
Chip Selects and Wait States
Product Specification
Figure 9
eZ80190
00h
.
54