EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 113

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

PS006614-1208
Note:
Slave Receive
If no ACK is received after transmitting a byte, the IFLG is set and the I2Cx_SR register
contains
If a STOP condition is detected after an ACK bit, the I
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter.
The I
bit (lsb = 0) after a START condition. The I
in the I2Cx_CTL register. The I2Cx_SR register then contains the status code
I
the GCE bit in the I2Cx_SAR register is set). The status code is then
When the I
ister), it transmits an ACK after the first address byte is received; however, no interrupt is
generated. IFLG is not required to be set and the status does not change. The I
ates an interrupt only after the second address byte is received. The I
bit and loads the status code, as described above.
I
the transmission of an address, and the slave address and write bit (or the general call
address if the CGE bit in the I2Cx_SAR register is set to 1) are received. The status code
in the I2Cx_SR register is
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the ACK bit in the I2Cx_CTL
transmitted and the IFLG bit is set after each byte is received. The
tains the status code
call address. The received data byte can be read from the
bit must be cleared to allow the transfer to continue. If a STOP condition or a repeated
START condition is detected after the ACK bit, the IFLG bit is set and the
ter contains status code
ing the transmission of an address, and the slave address and read bit are received. This
action is confirmed by the status code
cleared. After the I
I2Cx_SR register contains
I2Cx_DR register, the ACK bit is cleared when the IFLG is cleared. After the last byte is
transmitted, the IFLG is set and the I2Cx_SR register contains
IDLE state. The ACK bit must be set to 1 before SLAVE mode can be reentered.
I
The data byte to be transmitted is loaded into the I2Cx_DR register and the IFLG bit is
2
2
2
C also enters SLAVE RECEIVE mode when it receives the general call address
C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
2
C enters SLAVE RECEIVE mode when it receives its own slave address and a write
C0h
2
C contains a 10-bit slave address (signified by
. The I
2
2
C transmits the byte and receives an ACK, the IFLG bit is set and the
C then returns to the IDLE state.
80h
A0h
or
68h
B8h
.
90h
if the slave address is received or
. After the last byte to be transmitted is loaded into the
register
if SLAVE RECEIVE mode is entered with the general
B0h
is set to 1, then an ACK bit (Low level on SDA) is
2
in the I2Cx_SR register.
C transmits an ACK bit and sets the IFLG bit
2
C returns to the IDLE state.
I2Cx_DR
F0h
C8h
–
F7h
Product Specification
78h
register and the IFLG
. The I
I2Cx_SR
2
in the I2Cx_SAR reg-
C then sets the IFLG
70h
I2C Serial I/O Interface
if the general call
2
.
C returns to the
I2Cx_SR
register con-
60h
2
C gener-
00h
. The
regis-
(if
103