ISP1562BE STEricsson, ISP1562BE Datasheet - Page 37

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 46.
Address: Content of the base address register + 04h
Table 47.
Address: Content of the base address register + 08h
[1]
ISP1562_3
Product data sheet
Bit
1 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
CBSR
[1:0]
HcControl - Host Controller Control register bit description
HcCommandStatus - Host Controller Command Status register bit allocation
11.1.3 HcCommandStatus register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
Control Bulk Service Ratio: This specifies the service ratio of control EDs over bulk EDs. Before
processing any of the nonperiodic lists, the host controller must compare the ratio specified with its
internal count on how many nonempty control EDs are processed, in determining whether to continue
serving another control ED or switching to bulk EDs. The internal count must be retained when
crossing the frame boundary. After a reset, the HCD is responsible to restore this value.
00b — 1 : 1
01b — 2 : 1
10b — 3 : 1
11b — 4 : 1
This register is used by the host controller to receive commands issued by the HCD. It
also reflects the current status of the host controller. To the HCD, it appears as a ‘write to
set’ register. The host controller must ensure that bits written as logic 1 become set in the
register while bits written as logic 0 remain unchanged in the register. The HCD may issue
multiple distinct commands to the host controller without concern for corrupting previously
issued commands. The HCD has normal read access to all bits.
The SOC[1:0] field (bits 17 and 16 in the HcCommandStatus register) indicates the
number of frames with which the host controller has detected the scheduling overrun
error. This occurs when the periodic list does not complete before EOF. When a
scheduling overrun error is detected, the host controller increments the counter and sets
SO (bit 0 in the HcInterruptStatus register).
Table 47
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
shows the bit allocation of the HcCommandStatus register.
reserved
[1]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 03 — 14 November 2008
reserved
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
[1]
[1]
OCR
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
…continued
R/W
R/W
R/W
R/W
BLF
26
18
10
0
0
0
2
0
HS USB PCI host controller
R/W
R/W
R/W
R/W
CLF
25
17
0
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
SOC[1:0]
HCR
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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