ISP1562BE STEricsson, ISP1562BE Datasheet - Page 65

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 96.
Address: Content of the base address register + 24h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 16
15
14
13
12
11 to 6
5
4
The reserved bits should always be written with the reset value.
USBSTS - USB Status register bit description
Symbol
reserved
ASS
PSSTAT
RECL
HCH
reserved
IAA
HSE
R/W
ASS
R/W
23
15
R
0
0
7
0
reserved
Description
-
Asynchronous Schedule Status: Default = 0. The bit reports the current real status of the
asynchronous schedule. If this bit is logic 0, the status of the asynchronous schedule is disabled. If
this bit is logic 1, the status of the asynchronous schedule is enabled. The host controller is not
required to immediately disable or enable the asynchronous schedule when software changes ASE
(bit 5 in the USBCMD register). When this bit and the ASE bit have the same value, the
asynchronous schedule is either enabled (1) or disabled (0).
Periodic Schedule Status: Default = 0. This bit reports the current status of the periodic schedule.
If this bit is logic 0, the status of the periodic schedule is disabled. If this bit is logic 1, the status of
the periodic schedule is enabled. The host controller is not required to immediately disable or
enable the periodic schedule when software changes PSE (bit 4) in the USBCMD register. When
this bit and the PSE bit have the same value, the periodic schedule is either enabled (1) or disabled
(0).
Reclamation: Default = 0. This is a read-only status bit that is used to detect an empty
asynchronous schedule.
HC Halted: Default = 1. This bit is logic 0 when RS (bit 0) in the USBCMD register is logic 1. The
host controller sets this bit to logic 1 after it has stopped executing because the RS bit is set to
logic 0, either by software or by the host controller hardware. For example, on an internal error.
-
Interrupt on Asynchronous Advance: Default = 0. The system software can force the host
controller to issue an interrupt the next time the host controller advances the asynchronous
schedule by writing logic 1 to IAAD (bit 6) in the USBCMD register. This status bit indicates the
assertion of that interrupt source.
Host System Error: The host controller sets this bit when a serious error occurs during a host
system access, involving the host controller module. In a PCI system, conditions that set this bit
include PCI parity error, PCI master abort and PCI target abort. When this error occurs, the host
controller clears RS (bit 0 in the USBCMD register) to prevent further execution of the scheduled
TDs.
PSSTAT
[1]
R/W
R/W
22
14
R
0
0
6
0
RECL
R/W
IAA
21
13
R
R
0
0
5
0
Rev. 03 — 14 November 2008
HCH
HSE
R/W
R/W
20
12
R
0
1
4
0
reserved
[1]
R/W
R/W
R/W
FLR
19
11
0
0
3
0
PCD
R/W
R/W
R/W
18
10
0
0
2
0
reserved
HS USB PCI host controller
ERRINT
[1]
USB
R/W
R/W
R/W
17
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
USBINT
R/W
R/W
R/W
16
0
8
0
0
0
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