ISP1562BE STEricsson, ISP1562BE Datasheet - Page 54

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 81.
Address: Content of the base address register + 4Ch
Table 82.
Address: Content of the base address register + 4Ch
Table 83.
Address: Content of the base address register + 50h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 16
15 to 0
Bit
Symbol
Reset
Access
HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation
HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit description
Symbol
PPCM
[15:0]
DR[15:0]
HcRhStatus - Host Controller Root Hub Status register bit allocation
11.1.21 HcRhStatus register
CRWE
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
Description
Port Power Control Mask: Each bit indicates whether a port is affected by a global power control
command when Power Switching Mode is set. When set, only the power state of the port is affected
by per-port power control (Set/Clear Port Power). When cleared, the port is controlled by the global
power switch (Set/Clear Global Power). If the device is configured to global switching mode (Power
Switching Mode = 0), this field is not valid.
Bit 0 — Reserved
Bit 1 — Ganged-power mask on port 1
Bit 2 — Ganged-power mask on port 2
Device Removable: Each bit is dedicated to a port of the root hub. When cleared, the attached
device is removable. When set, the attached device is not removable.
Bit 0 — Reserved
Bit 1 — Device attached to port 1
Bit 2 — Device attached to port 2
This register is divided into two parts. The lower word of a DWORD represents the Hub
Status field, and the upper word represents the Hub Status Change field. Reserved bits
must always be written as logic 0.
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Rev. 03 — 14 November 2008
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
PPCM[15:8]
Table 83
PPCM[7:0]
DR[15:8]
DR[7:0]
reserved
shows the bit allocation of the register.
R/W
R/W
R/W
R/W
27
19
11
27
R
0
0
0
3
0
0
[1]
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
HS USB PCI host controller
R/W
R/W
R/W
R/W
R/W
25
17
25
0
1
9
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
R/W
R/W
R/W
R/W
24
16
24
0
0
8
0
0
0
0
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