ISP1562BE STEricsson, ISP1562BE Datasheet - Page 71

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 107. CONFIGFLAG - Configure Flag register bit description
Address: Content of the base address register + 60h
Table 108. PORTSC 1, 2 - Port Status and Control 1, 2 register bit allocation
Address: Content of the base address register + 64h + (4
[1]
ISP1562_3
Product data sheet
Bit
31 to 1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
reserved
CF
11.3.8 PORTSC registers 1, 2
reserved
SUSP
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
-
Configure Flag: The host software sets this bit as the last action in its process of configuring the host
controller. This bit controls the default port-routing control logic.
0 — Port routing control logic default-routes each port to an implementation-dependent classic host
controller.
1 — Port routing control logic default-routes all ports to this host controller.
reserved
The Port Status and Control (PORTSC) register is in the auxiliary power well. It is only
reset by hardware when the auxiliary power is initially applied or in response to a host
controller reset. The initial conditions of a port are:
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until power is stable
on the port; maximum delay is 20 ms from the transition. For bit allocation, see
•
•
WKOC_E
No device connected
Port disabled
[1]
FPR
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
CNNT_E
WKDS
OCC
R/W
R/W
R/W
PO
29
21
13
R
0
0
1
5
0
Rev. 03 — 14 November 2008
WKCNNT_
Port Number
OCA
R/W
R/W
R/W
PP
28
20
12
R
E
0
0
0
4
0
reserved
[1]
PEDC
R/W
R/W
R/W
R/W
27
19
11
1) where Port Number is 1, 2
0
0
0
3
0
LS[1:0]
PED
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI host controller
PTC[3:0]
reserved
ECSC
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
[1]
Table
ECCS
R/W
R/W
PR
24
16
R
R
0
0
8
0
0
0
70 of 93
108.