ISP1562BE STEricsson, ISP1562BE Datasheet - Page 47

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 66.
Address: Content of the base address register + 2Ch
Table 67.
Address: Content of the base address register + 30h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4 BCED[27:0] Bulk Current ED: This is advanced to the next ED after the host controller has served the current
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
reserved
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description
HcDoneHead - Host Controller Done Head register bit allocation
11.1.13 HcDoneHead register
R/W
R/W
R/W
R/W
R/W
R/W
23
15
31
23
15
0
0
7
0
0
0
0
Description
ED. The host controller continues processing the list from where it left off in the last frame. When it
reaches the end of the bulk list, the host controller checks CLF (bit 1 of HcCommandStatus). If the
CLF bit is not set, nothing is done. If the CLF bit is set, it copies the content of HcBulkHeadED to
HcBulkCurrentED and clears the CLF bit. The HCD can modify this register only when BLE (bit 5 in
the HcControl register) is cleared. When HcControl is set, the HCD reads the instantaneous value of
this register. This is initially set to logic 0 to indicate the end of the bulk list.
-
The HcDoneHead register contains the physical address of the last completed TD that
was added to the done queue. In a normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
of the register.
R/W
R/W
R/W
R/W
R/W
R/W
22
14
30
22
14
0
0
6
0
0
0
0
BCED[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
21
13
29
21
13
0
0
5
0
0
0
0
Rev. 03 — 14 November 2008
R/W
R/W
R/W
R/W
R/W
R/W
20
12
28
20
12
0
0
4
0
0
0
0
BCED[19:12]
BCED[11:4]
DH[27:20]
DH[19:12]
DH[11:4]
R/W
R/W
R/W
R/W
R/W
R/W
19
11
27
19
11
0
0
3
0
0
0
0
Table 67
R/W
R/W
R/W
R/W
R/W
R/W
18
10
26
18
10
0
0
2
0
0
0
0
reserved
HS USB PCI host controller
shows the bit allocation
[1]
R/W
R/W
R/W
R/W
R/W
R/W
17
25
17
0
9
0
1
0
0
0
9
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
R/W
R/W
R/W
R/W
R/W
16
24
16
0
8
0
0
0
0
0
8
0
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