ISP1562BE STEricsson, ISP1562BE Datasheet - Page 58

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 86.
Address: Content of the base address register + 54h
ISP1562_3
Product data sheet
Bit
4
3
2
1
0
Symbol
PRS
POCI
PSS
PES
CCS
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description
Description
On read Port Reset Status: When this bit is set by a write to Set Port Reset, port reset signaling is
asserted. When reset is completed and PRSC is set, this bit is cleared.
0 — Port reset signal is inactive.
1 — Port reset signal is active.
On write Set Port Reset: The HCD can set the port reset signaling by writing logic 1 to this bit.
Writing logic 0 has no effect. If CCS is cleared, this write does not set PRS (Port Reset Status) but
instead sets CCS. This informs the driver that it attempted to reset a disconnected port.
On read Port Overcurrent Indicator: This bit is valid only when the root hub is configured to show
overcurrent conditions are reported on a per-port basis. If the per-port overcurrent reporting is not
supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an
overcurrent condition exists on this port.
0 — No overcurrent condition.
1 — Overcurrent condition detected.
On write Clear Suspend Status: The HCD can write logic 1 to initiate a resume. Writing logic 0 has
no effect. A resume is initiated only if PSS (Port Suspend Status) is set.
On read Port Suspend Status: This bit indicates whether the port is suspended or is in the resume
sequence. It is set by a Set Suspend State write and cleared when PSSC (Port Suspend Status
Change) is set at the end of the resume interval. This bit is not set if CCS (Current Connect Status) is
cleared. This bit is also cleared when PRSC is set at the end of the port reset or when the host
controller is placed in the USBRESUME state. If an upstream resume is in progress, it will propagate
to the host controller.
0 — Port is not suspended.
1 — Port is suspended.
On write Set Port Suspend: The HCD can set the PSS (Port Suspend Status) bit by writing logic 1 to
this bit. Writing logic 0 has no effect. If CCS is cleared, this write does not set PSS; instead it sets
CSS. This informs the driver that it attempted to suspend a disconnected port.
On read Port Enable Status: This bit indicates whether the port is enabled or disabled. The root hub
may clear this bit when an overcurrent condition, disconnect event, switched-off power or operational
bus error is detected. This change also causes Port Enabled Status Change to be set. The HCD can
set this bit by writing Set Port Enable and clear it by writing Clear Port Enable. This bit cannot be set
when CCS (Current Connect Status) is cleared. This bit is also set on completing a port reset when
Reset Status Change is set or on completing a port suspend when Suspend Status Change is set.
0 — Port is disabled.
1 — Port is enabled.
On write Set Port Enable: The HCD can set PES (Port Enable Status) by writing logic 1. Writing
logic 0 has no effect. If CCS is cleared, this write does not set PES, but instead sets CSC (Connect
Status Change). This informs the driver that it attempted to enable a disconnected port.
On read Current Connect Status: This bit reflects the current state of the downstream port.
0 — No device connected.
1 — Device connected.
On write Clear Port Enable: The HCD can write logic 1 to this bit to clear the PES (Port Enable
Status) bit. Writing logic 0 has no effect. The CCS bit is not affected by any write.
Remark: This bit always reads logic 1 when the attached device is nonremovable
(DeviceRemovable[NDP]).
Rev. 03 — 14 November 2008
HS USB PCI host controller
© NXP B.V. 2008. All rights reserved.
ISP1562
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