ISP1562BE STEricsson, ISP1562BE Datasheet - Page 68

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 100. FRINDEX - Frame Index register bit description
Address: Content of the base address register + 2Ch
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 14
13 to 0
The reserved bits should always be written with the reset value.
Symbol
reserved
FRINDEX [13:0]
11.3.5 PERIODICLISTBASE register
R/W
R/W
R/W
23
15
0
0
7
0
reserved
Table 101. N based value of FLS[1:0]
The Periodic Frame List Base Address (PERIODLISTBASE) register contains the
beginning address of the periodic frame list in the system memory. If the host controller is
in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of the HCCPARAMS register), the
most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. For details on the CTRLDSSEGMENT register, refer to
Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 . The
system software loads this register before starting the schedule execution by the host
controller. The memory structure referenced by this physical memory pointer is assumed
as 4 kB aligned. The contents of this register are combined with the FRINDEX register to
enable the host controller to step through the periodic frame list in sequence.
The bit allocation is given in
FLS[1:0]
00b
01b
10b
11b
[1]
R/W
R/W
R/W
22
14
Description
-
Frame Index: Bits in this register are used for the frame number in the SOF packet and as
the index into the frame list. The value in this register increments at the end of each time
frame. For example, microframe. The bits used for the frame number in the SOF token are
taken from bits 13 to 3 of this register. Bits N to 3 are used for the frame list current index.
This means that each location of the frame list is accessed eight times, frames or
microframes, before moving to the next index.
Table 101
register).
0
0
6
0
illustrates values of N based on the value of FLS[1:0] (bits 3 to 2 in the USBCMD
R/W
R/W
R/W
21
13
0
0
5
0
Rev. 03 — 14 November 2008
Table
Number elements
1024
512
256
reserved
R/W
R/W
R/W
20
12
0
0
4
0
FRINDEX[7:0]
102.
reserved
[1]
R/W
R/W
R/W
19
11
FRINDEX[13:8]
0
0
3
0
R/W
R/W
R/W
18
10
0
0
2
0
HS USB PCI host controller
N
12
11
10
-
R/W
R/W
R/W
17
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
R/W
R/W
16
0
8
0
0
0
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