ISP1562BE STEricsson, ISP1562BE Datasheet - Page 64

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 94.
Address: Content of the base address register + 20h
Table 95.
Address: Content of the base address register + 24h
ISP1562_3
Product data sheet
Bit
5
4
3 to 2
1
0
Bit
Symbol
Reset
Access
USBCMD - USB Command register bit description
Symbol
ASE
PSE
FLS[1:0]
HCRESET
RS
USBSTS - USB Status register bit allocation
11.3.2 USBSTS register
R/W
31
0
The USB Status (USBSTS) register indicates pending interrupts and various states of the
host controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears register bits by writing ones to them. The bit allocation is
given in
Description
Asynchronous Schedule Enable: Default = 0. This bit controls whether the host controller skips
processing the asynchronous schedule.
0 — Do not process the asynchronous schedule.
1 — Use the ASYNCLISTADDR register to access the asynchronous schedule.
Periodic Schedule Enable: Default = 0. This bit controls whether the host controller skips
processing the periodic schedule.
0 — Do not process the periodic schedule.
1 — Use the PERIODICLISTBASE register to access the periodic schedule.
Frame List Size: Default = 00b. This field is read and write only if PFLF (bit 1) in the
HCCPARAMS register is set to logic 1. This field specifies the size of the frame list. The size the
frame list controls which bits in the Frame Index register must be used for the frame list current
index.
00b — 1024 elements (4096 bytes)
01b — 512 elements (2048 bytes)
10b — 256 elements (1024 bytes) for small environments
11b — reserved
Host Controller Reset: This control bit is used by the software to reset the host controller. The
effects of this on Root Hub registers are similar to a chip hardware reset. Setting this bit causes
the host controller to reset its internal pipelines, timers, counters, state machines, and so on, to
their initial values. Any transaction currently in progress on USB is immediately terminated. A USB
reset is not driven on downstream ports. This reset does not affect the PCI Configuration registers.
All operational registers, including port registers and port state machines, are set to their initial
values. Port ownership reverts to the companion host controller(s). The software must re-initialize
the host controller to return it to an operational state. This bit is cleared by the host controller when
the reset process is complete. Software cannot terminate the reset process early by writing logic 0
to this register. Software must check that bit HCH is logic 0 before setting this bit. Attempting to
reset an actively running host controller results in undefined behavior.
Run/Stop: 1 = Run. 0 = Stop. When set, the host controller executes the schedule. The host
controller continues execution as long as this bit is set. When this bit is cleared, the host controller
completes the current and active transactions in the USB pipeline, and then halts. Bit HCH
indicates when the host controller has finished the transaction and has entered the stopped state.
Software must check that the HCH bit is logic 1, before setting this bit.
R/W
30
0
Table
95.
R/W
29
0
Rev. 03 — 14 November 2008
R/W
28
0
reserved
…continued
[1]
R/W
27
0
R/W
26
0
HS USB PCI host controller
R/W
25
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
24
0
63 of 93