ISP1562BE STEricsson, ISP1562BE Datasheet - Page 90

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 53. HcInterruptDisable - Host Controller
Table 54. HcInterruptDisable - Host Controller
Table 55. HcHCCA - Host Controller Communication
Table 56. HcHCCA - Host Controller Communication
Table 57. HcPeriodCurrentED - Host Controller
Table 58. HcPeriodCurrentED - Host Controller
Table 59. HcControlHeadED - Host Controller Control
Table 60. HcControlHeadED - Host Controller Control
Table 61. HcControlCurrentED - Host Controller
Table 62. HcControlCurrentED - Host Controller
Table 63. HcBulkHeadED - Host Controller Bulk Head
Table 64. HcBulkHeadED - Host Controller Bulk Head
Table 65. HcBulkCurrentED - Host Controller Bulk
Table 66. HcBulkCurrentED - Host Controller Bulk
Table 67. HcDoneHead - Host Controller Done Head
Table 68. HcDoneHead - Host Controller Done Head
Table 69. HcFmInterval - Host Controller Frame
Table 70. HcFmInterval - Host Controller Frame
Table 71. HcFmRemaining - Host Controller Frame
Table 72. HcFmRemaining - Host Controller Frame
Table 73. HcFmNumber - Host Controller Frame
ISP1562_3
Product data sheet
Interrupt Enable register bit description . . . . . .39
Interrupt Disable register bit allocation . . . . . .40
Interrupt Disable register bit description . . . . .41
Area register bit allocation . . . . . . . . . . . . . . . .42
Area register bit description . . . . . . . . . . . . . . .42
Period Current Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Period Current Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .43
Head Endpoint Descriptor register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Head Endpoint Descriptor register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Control Current Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Control Current Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44
Endpoint Descriptor register bit allocation . . . .45
Endpoint Descriptor register bit description . . .45
Current Endpoint Descriptor register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Current Endpoint Descriptor register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
register bit allocation . . . . . . . . . . . . . . . . . . . .46
register bit description . . . . . . . . . . . . . . . . . . .47
Interval register bit allocation . . . . . . . . . . . . . .47
Interval register bit description . . . . . . . . . . . . .48
Remaining register bit allocation . . . . . . . . . . .48
Remaining register bit description . . . . . . . . . .49
Number register bit allocation . . . . . . . . . . . . .49
Rev. 03 — 14 November 2008
Table 74. HcFmNumber - Host Controller Frame
Table 75. HcPeriodicStart - Host Controller Periodic
Table 76. HcPeriodicStart - Host Controller Periodic
Table 77. HcLSThreshold - Host Controller Low-Speed
Table 78. HcLSThreshold - Host Controller Low-Speed
Table 79. HcRhDescriptorA - Host Controller Root Hub
Table 80. HcRhDescriptorA - Host Controller Root Hub
Table 81. HcRhDescriptorB - Host Controller Root Hub
Table 82. HcRhDescriptorB - Host Controller Root Hub
Table 83. HcRhStatus - Host Controller Root Hub
Table 84. HcRhStatus - Host Controller Root Hub
Table 85. HcRhPortStatus[4:1] - Host Controller Root
Table 86. HcRhPortStatus[4:1] - Host Controller Root
Table 87. CAPLENGTH/HCIVERSION - Capability
Table 88. CAPLENGTH/HCIVERSION - Capability
Table 89. HCSPARAMS - Host Controller Structural
Table 90. HCSPARAMS - Host Controller Structural
Table 91. HCCPARAMS - Host Controller Capability
Table 92. HCCPARAMS - Host Controller Capability
Table 93. USBCMD - USB Command register bit
Table 94. USBCMD - USB Command register bit
Table 95. USBSTS - USB Status register bit allocation . 63
Table 96. USBSTS - USB Status register bit description 64
Table 97. USBINTR - USB Interrupt Enable register bit
Table 98. USBINTR - USB Interrupt Enable register bit
Table 99. FRINDEX - Frame Index register bit allocation 66
Number register bit description . . . . . . . . . . . . 49
Start register bit allocation . . . . . . . . . . . . . . . 50
Start register bit description . . . . . . . . . . . . . . 50
Threshold register bit allocation . . . . . . . . . . . 50
Threshold register bit description . . . . . . . . . . 51
Descriptor A register bit allocation . . . . . . . . . 51
Descriptor A register bit description . . . . . . . . 52
Descriptor B register bit allocation . . . . . . . . . 53
Descriptor B register bit description . . . . . . . . 53
Status register bit allocation . . . . . . . . . . . . . . 53
Status register bit description . . . . . . . . . . . . . 54
Hub Port Status[4:1] register bit allocation . . . 55
Hub Port Status[4:1] register bit description . . 55
Length/Host Controller Interface Version
Number register bit allocation . . . . . . . . . . . . . 58
Length/Host Controller Interface Version
Number register bit description . . . . . . . . . . . . 58
Parameters register bit allocation . . . . . . . . . . 59
Parameters register bit description . . . . . . . . . 59
Parameters register bit allocation . . . . . . . . . . 60
Parameters register bit description . . . . . . . . . 60
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HS USB PCI host controller
© NXP B.V. 2008. All rights reserved.
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