EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 295

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter Revision Dates ......................................................................... xiii
About This Handbook ............................................................................. xv
Section I. Clock Management
Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices
Altera Corporation
How to Find Information ...................................................................................................................... xv
How to Contact Altera ........................................................................................................................... xv
Typographic Conventions .................................................................................................................... xvi
Revision History ....................................................................................................................... Section I–1
Introduction ............................................................................................................................................ 1–1
Enhanced PLLs ....................................................................................................................................... 1–5
Fast PLLs ............................................................................................................................................... 1–31
Clocking ................................................................................................................................................ 1–39
Board Layout ........................................................................................................................................ 1–50
Clock Multiplication & Division .................................................................................................... 1–9
External Clock Outputs ................................................................................................................. 1–10
Clock Feedback ............................................................................................................................... 1–14
Phase Shifting ................................................................................................................................. 1–14
Lock Detect ...................................................................................................................................... 1–15
Programmable Duty Cycle ........................................................................................................... 1–16
General Advanced Clear & Enable Control ............................................................................... 1–16
Programmable Bandwidth ............................................................................................................ 1–18
Clock Switchover ............................................................................................................................ 1–25
Spread-Spectrum Clocking ........................................................................................................... 1–25
PLL Reconfiguration ...................................................................................................................... 1–30
Enhanced PLL Pins ........................................................................................................................ 1–30
Clock Multiplication & Division .................................................................................................. 1–34
External Clock Outputs ................................................................................................................. 1–34
Phase Shifting ................................................................................................................................. 1–35
Programmable Duty Cycle ........................................................................................................... 1–36
Control Signals ................................................................................................................................ 1–36
Pins ................................................................................................................................................... 1–37
Global & Hierarchical Clocking ................................................................................................... 1–39
Clock Input Connections ............................................................................................................... 1–41
Clock Output Connections ............................................................................................................ 1–43
VCCA & GNDA ............................................................................................................................. 1–50
Contents
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