EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 511

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 5–25. Input Timing Waveform
Note to
(1)
Altera Corporation
July 2005
Input Clock
(Differential
Signal)
Input Data
The timing specifications are referenced at a 100-mV differential voltage.
Figure
5–25:
t sw0 (min)
Previous Cycle
t sw0 (max)
bit 0
t sw1 (min)
t sw1 (max)
t sw2 (min)
bit 1
Input Timing Waveform
Figure 5–25
relationship between the clock cycle and the incoming serial data. For a
functional description of the SERDES, see
Operation” on page
t sw2 (max)
t sw3 (min)
t sw3 (max)
Note (1)
bit 2
MSB
t sw4 (min)
t sw4 (max)
illustrates the essential operations and the timing
t sw5 (min)
bit 3
t sw5 (max)
High-Speed Differential I/O Interfaces in Stratix Devices
t sw6 (min)
5–6.
t sw6 (max)
bit 4
t sw7 (min)
t sw7 (max)
bit 5
Current Cycle
bit 6
Stratix Device Handbook, Volume 2
“Principles of SERDES
bit 7
LSB
Cycle
Next
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