EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 538

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Software Support
Figure 5–42. Page 3 of the Transmitter altlvds MegaWizard Plug-In Manager
5–66
Stratix Device Handbook, Volume 2
Number of Channels
The What is the number of channels? parameter specifies the number of
transmitter channels required and the width of the tx_in port. You can
have more than 20 channels in a transmitter or receiver module by typing
in the required number instead of choosing a number from the drop
down menu, which only has selections of up to 20 channels.
Deserialization Factor
The What is the deserialization factor? parameter specifies the number
of bits per channel. The transmitter block supports deserialization factors
of 4, 7, 8, and 10. Based on the factor specified, the Quartus II software
determines the multiplication and/or division factor for the LVDS PLL in
order to serialize the data.
Table 5–5 on page 5–32
parallel data for the n
[(J
×
n) – 1]) to the LSB (rx_out bit [J
th
lists the differential bit naming convention. The
channel spans from the MSB (rx_out bit
×
(n – 1)]), where J is the
Altera Corporation
July 2005