EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 632

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Discrete Cosine Transform (DCT)
Figure 7–32. A 2-D DCT is a Separable Transform
7–54
Stratix Device Handbook, Volume 2
This section uses a standard algorithm proposed in [1].
shows the flow graph for the algorithm. This is similar to the butterfly
computation of the fast fourier transform (FFT). Similar to the FFT
algorithms, the DCT algorithm reduces the complexity of the calculation
by decomposing the computation into successively smaller DCT
components. The even coefficients (y
upper half and the odd coefficients (y
result of the decomposition, the output is reordered as well.
Figure 7–33. Implementing an N=8 Fast DCT
x
x
x
x
x
x
x
x
1
2
4
5
6
0
3
7
S3
S3
S3
a
b
n
2
1
Stage 1
.
.
.
C m1
C m2
C mn
.
.
.
.
Multiplied by -1
Sum a and b
Stage 2
y
k
Stage 3
Stage 3 output (S3)
Multiply-addition block
y
Matrix coefficent (C mn )
where
k
= c
0
m1
1
, y
, y
s
c
C 4
C 6
C 2 C 6
2
C 7
C 5
C 3
C 1
3 1
x
3
, y
= cos
, y
+ c
-C 2
4
-C 5
-C 1
-C 7
5
C 3
, y
, y
m2
Stage 4
6
(
s
7
) are calculated in the
-C 1
16
x
C 3
C 5
3 2
C 7
) in the lower half. As a
)
+ ... + c
-C 1
-C 5
C 7
C 3
Altera Corporation
mn
Figure 7–33
y
y
September 2004
y
y
y
y
y
y
s
0
6
2
3
7
3 n
4
1
5