EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 492

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Differential I/O Interface & Fast PLLs
5–20
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
DIFFIOCLK14
DIFFIOCLK15
DIFFIOCLK16
Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 2 of 2)
Output Signal
PLLs 5, 6, 11, and 12 are not fast PLLs.
The input clock for PLLs used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be
driven by a dedicated clock pin (CLK[3..0] and CLK[8..11]) or the corner pins that clock the corner PLLs
(FPLL[10..7]CLK).
Table
5–4:
PLL 1
Fast PLL Specifications
You can drive the fast PLLs by an external pin or any one of the sectional
clocks [21..0]. You can connect the clock input directly to local or global
clock lines, as shown in
inputs to the fast PLL’s input multiplexer for the receiver PLL. You can
only use the sectional clock inputs in the transmitter only mode or as a
general purpose PLL.
All Stratix Devices
PLL 2
PLL 3
PLL 4
Figure
5–14. You cannot use the sectional-clock
PLL 7
EP1S30 to EP1S80 Devices Only
Notes
PLL 8
(1),
(2)
PLL 9
Altera Corporation
v
July 2005
PLL 10
v
v