EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 601

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 7–13. Implementation of the Polyphase Interpolation Filter (I=4)
Notes to
(1)
(2)
(3)
Altera Corporation
September 2004
Clock input
(1x clock)
The 1
The 4 clock feeds the input registers for the filter coefficients and other optional registers in the DSP block. See
Note
To increase the DSP block performance, include the pipeline, and output registers. See
Figure
(3).
clock feeds the input data shiftin register chain.
7–13:
PLL
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
1x clock
4x clock
Filter coefficients
RAM / ROM 0
RAM / ROM 2
RAM / ROM 1
Data input
h(3)
h(2)
h(0)
h(1)
x(n)
x x
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Stratix Device Handbook, Volume 2
Notes
(1), (2),
Note (1)
Figure 7–3
DSP block
(3)
Note (2)
for the details.
Filter output
y(n)
7–23