EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 469

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 4–24. Floorplan View Window
Altera Corporation
June 2006
Auto Placement & Verification of Selectable I/O Standards
The Quartus II software automatically verifies the placement for all I/O
and V
■
■
■
■
■
Automatically places I/O pins of different V
pin assignments in separate I/O banks and enables the V
these I/O banks.
Verifies that voltage-referenced I/O pins requiring different V
levels are not placed in the same bank.
Reports an error message if the current limit is exceeded for a Stratix
or Stratix GX power bank, as determined by the equation
documented in
Reserves the unused high-speed differential I/O channels and
regular user I/O pins in the high-speed differential I/O banks when
any of the high-speed differential I/O channels are being used.
Automatically assigns V
requirements are met and I/O standards are placed properly.
REF
pins and performs the following actions.
Selectable I/O Standards in Stratix & Stratix GX Devices
“DC Guidelines” on page
REF
pins and I/O pins such that the current
Stratix Device Handbook, Volume 2
4–35.
REF
standards without
REF
pins of
REF
4–41