EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 708

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

PLLs & Clock Networks
10–24
Stratix Device Handbook, Volume 2
APEX II, APEX 20KE, and APEX 20KC devices have only one external
clock output available per PLL. Therefore, when retargeting an APEX II,
APEX 20KE, or APEX 20KC design that uses PLLs in zero delay buffer
mode or external feedback mode to a Stratix or Stratix GX device, you
should replace instances of the altclklock megafunction. If an
APEX II, APEX 20KE, or APEX 20KC altclklock module only uses one
PLL clock output (internal or external) and is compiled to target a Stratix
or Stratix GX device, the design compiles successfully with a warning
that the design uses the Stratix or Stratix GX PLL external clock output,
extclk0. However, if the APEX II, APEX 20KE, or APEX 20KC PLL has
more than one PLL clock output, you must replace instances of the
altclklock megafunction with the altpll megafunction because the
Quartus II Compiler does not know which PLL clock output is fed to an
external output pin or fed back to the Stratix or Stratix GX device fbin
pin. For example, if an APEX II, APEX 20KE, or APEX 20KC design with
an altclklock megafunction uses the clock0 output port to feed the
external clock output pin and the clock1 output port to feed the internal
logic array, the Quartus II software generates an error during
compilation and you must use the MegaWizard Plug-In Manager to
instantiate the altpll megafunction. By using the altpll
megafunction, you can choose which of the four external clock outputs to
use and take advantage of the new Stratix and Stratix GX PLL features
now available in the zero delay buffer mode or external feedback mode.
Timing Analysis
When the Quartus II software performs a timing analysis for APEX II,
APEX 20KE, or APEX 20KC designs, PLL clock settings override the
project clock settings. However, during timing analysis for Stratix and
Stratix GX designs using PLLs, the project clock settings override the PLL
input clock frequency and duty cycle settings. The MegaWizard Plug-In
Manager does not use the project clock settings to determine the altpll
parameters. This saves time with designs that use features such as clock
switchover or PLL reconfiguration because the Quartus II software can
perform a timing analysis without recompiling the design. It is important
to note the following:
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A warning during compilation reports that the project clock settings
overrides the PLL clock settings.
The project clock setting overrides the PLL clock settings for timing-
driven compilation.
The compiler will check the lock frequency range of the PLL. If the
frequency specified in the project clock settings is outside the lock
frequency range, the PLL clock settings will not be overridden.
Performing a timing analysis without recompiling your design does
not change the programming files. You must recompile your design
to update the programming files.
Altera Corporation
July 2005