EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 608

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Finite Impulse Response (FIR) Filters
Figure 7–17. Implementation of the Polyphase Decimation Filter (D=4)
Notes to
(1)
(2)
(3)
7–30
Stratix Device Handbook, Volume 2
Clock input
(1x clock)
Data input
The 1
The 4
optional registers in the DSP block (see
To increase the DSP block performance, include the pipeline, and output registers. See
the details.
x(n)
x x
Figure
clock feeds the shift register for the data, the input registers for both the data and filter coefficients, the other
clock feeds the register after the accumulator block.
D
D
D
D
D
D
D
7–17:
Q
Q
Q
Q
Q
Q
Q
PLL
D
D
D
D
4x clock
1x clock
D
D
Q
Q
Q
Q
Q
Q
coefficients
Note
Filter
ROM
ROM
ROM
(3)), and the accumulator block.
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Note (2)
Notes
(1), (2),
DSP block
Figure 7–3 on page 7–8
(3)
Note (1)
Altera Corporation
September 2004
D
Filter output
Q
y(n)
for