EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 505

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
t
Timing unit interval (TUI)
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t
t
FALL
HSDR
DUTY
LOCK
Table 5–6. High-Speed Timing Specifications & Terminology (Part 2 of 2)
High-Speed Timing Specification
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Maximum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges,
including t
measurement.
The period of time during which the data must be valid in order for you to
capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.
SW = t
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
SW
CO
(max) – t
High-Speed Differential I/O Interfaces in Stratix Devices
variation and clock skew. The clock is included in the TCCS
SW
(min).
C
/w).
Terminology
Stratix Device Handbook, Volume 2
HSDR
= 1/TUI).
5–33