EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 350

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Clocking
1–40
Stratix Device Handbook, Volume 2
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. All resources within the device—IOEs, LEs, DSP blocks, and
all memory blocks—can use the global clock networks as clock sources.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin.
Internal logic can also drive the global clock networks for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout.
pins driving global clock networks.
Figure 1–19. Global Clocking
Regional Clock Network
There are four regional clock networks within each quadrant of the
Stratix or Stratix GX device that are driven by the same dedicated
CLK[15..0] input pins or from PLL outputs. From a top view of the
silicon, RCLK[0..3] are in the top-left quadrant, RCLK[8..11] are in
the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Figure 1–19
CLK[15..12]
Global Clock [15..0]
shows the 16 dedicated CLK
Altera Corporation
CLK[11..8]
July 2005