RC82562EP Intel, RC82562EP Datasheet - Page 105

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.4.3
6.4.3.1
6.4.3.1.1
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
During Phase 1, the linear feedback shift register (LFSR), exponential backoff time-out, slot time,
and collision counters are checked. The test is performed in the following manner:
During Phase 2, the test is performed in the following steps:
If Step 4 is successful, then a passed status is returned; otherwise, a failed status is returned.
Receive Operation
Receive Frame Area
The 8255x supports the concept of a receive frame area (RFA). The RFA is the list of free receive
resources and consists of Receive Frame Descriptors (RFDs). The RFDs contain data buffers
capable of holding maximum Ethernet size packets immediately following the RFD header. This
constitutes the simplified memory model. Each receive frame is described by one RFD.
Simplified RFA Structure
In the simplified RFA structure, the data portion of the received frame (including the Ethernet
header) is part of the RFD and is located in contiguous memory immediately after the size field in
the RFD. The simplified memory structure is shown in the figure below.
1. All counters and shift registers are reset simultaneously.
2. The unit starts counting and shifting the registers.
3. The exponential backoff shift register reaches all ones.
4. The unit checks the exponential backoff shift register for all ones when the LFSR content is all
5. The unit stops counting when the LFSR (30 bits) reaches a specific state, and the exponential
6. Phase 1 is successful if the 10 least significant bits (when applicable) of all four counters are
1. The exponential backoff shift register, LFSR, and all counters are reset.
2. The exponential backoff logic is temporarily configured accordingly:
3. Transmission and collisions are emulated internally.
4. If the most significant bit of exponential backoff shift register is 0, then step 3 is repeated.
ones in its 10 least significant bits.
backoff counter (10 bits) wraps from all ones to all zeroes. Simultaneously, the slot time
counter switches from 01111111111 to 10000000000, and the collision counter (4 bits) wraps
from all ones to all zeroes.
all zero.
a. SLOT-TIME = 3h
b. LIN-PRIO = 6h
c. EXP-PRIO = 3h
d. BOF-MET = 0h
Host Software Interface
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