RC82562EP Intel, RC82562EP Datasheet - Page 43

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 13. SCB Status Word Bits Descriptions
malfunctions. It is simply ignored by the device. Also, any 0 bits in the interrupt acknowledge
command have no effect, whether the interrupt is pending or not.
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Symbol
CX/TNO
FR
CNA
RNR
MDI
SWI
Reserved
FCP
Description
This bit indicates that the CU finished executing a command with its interrupt bit
set.
The 82557 includes a TNO feature where the device can be configured to assert
this interrupt when a transmit command is completed with a status of not okay.
The TNO interrupt feature is not available in the 82558 or later devices.
This bit indicates that the RU has finished receiving a frame or the header portion
of a frame if the device is in header RFD mode.
This bit indicates when the CU has left the active state or has entered the idle state.
There are 2 distinct states of the CU. When the device is configured to generate
CNA interrupt, the interrupt is activated when the CU leaves the active state and
enters either the idle or suspended state. When the device is configured to
generate CI interrupt, an interrupt will be generated only when the CU enters the
idle state.
This bit indicates when the RU leaves the ready state. The RU may leave the ready
state due to an RU Abort command or because there are no available resources or
if the RU filled an RFD with its suspend bit set.
This bit indicates when an MDI read or write cycle has completed. This interrupt
only occurs if it is enabled through the interrupt enable bit (bit 29) in the MDI
Control Register of the CSR.
This bit is used for software generated interrupts. In some cases, software may
need to generate an interrupt to re-enter the ISR.
This bit is reserved and should not be used.
This bit is used for flow control pause interrupt. It is present in the 82558 and later
devices.
This bit is not used on the 82557 and should be treated as a reserved bit.
Host Software Interface
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