RC82562EP Intel, RC82562EP Datasheet - Page 39

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.3
6.3.1
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 10. Alignment Requirements for 8255x Data Structures
As the table above indicates, the 8255x have the same alignment restrictions with one exception:
The 82558, and 82559 have a limited capability to support odd byte aligned buffers.
Controlling the Device
Software issues control commands to the CU and RU through the SCB, which is part of the CSR.
The CPU instructs the device to activate, suspend, resume or idle the CU or RU by placing the
appropriate control command in the CU or RU control field. A CPU write access to the SCB causes
the device to read the SCB, including the Status word, Command word, CU and RU Control fields,
and the SCB General Pointer. Activating the CU causes the device to start executing the CBL.
When execution is completed the device updates the SCB with the CU status then interrupts the
CPU if it is configured. Activating the RU causes the device to access the RFA and go into the
ready state for frame reception. When a frame is received the RU updates the SCB with the RU
status and interrupts the CPU. It also automatically advances to the next free RFD in the RFA. This
interaction between the CPU and the device can continue until a software or selective reset is
issued to the device, at which point the initialization process must be executed again. The CPU can
also perform certain controller functions directly through a CPU port interface.
Control / Status Registers (CSR)
The Control/Status Registers make up the CSR space. The basic registers are the SCB Command
word, SCB Status word, SCB General Pointer, Port interface, EEPROM Control register, and MDI
Control register. Additionally, the 82558 and later devices also contain registers for flow control,
power management, etc. All of these registers are shown in the table below. Registers new to the
82558 are lightly shaded, and registers new to the 82559 (at offset 1Ch and beyond) are darkly
shaded. Accessing these higher offset areas in older devices has an unpredictable effect and may
cause errors.
Port Self-Test
Port Dump
CSR and SCB
TxCB (buffer of TxCB in
simplified mode)
TBD
Transmit Buffer (flexible mode
only)
RFD (buffer of RFD in
simplified mode)
Data Structure
Paragraph aligned (16-byte)
Paragraph aligned (16-byte)
Address allocated by the BIOS. No other alignment requirements.
Word (even address) aligned (2-byte aligned). However, Dword (4-byte
aligned) structures are more efficient.
Word (even address) aligned (2-byte aligned). However, Dword (4-byte
aligned) structures are more efficient.
Byte aligned (address can be odd or even).
Word (even address) aligned (2-byte aligned). However, Dword (4-byte
aligned) structures are more efficient.
NOTE: In an MWI aware system, for best performance RFDs should be
allocated so that the RFD data area (if not zero) is cache line
aligned.
Alignment Requirements
Host Software Interface
31