RC82562EP Intel, RC82562EP Datasheet - Page 162

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

82550 and 82551 Specific Information
154
Table 69. IPCB Fields
Field Name
Total TCP/UDP
Payload
TCP Header
Offset
IP Header Offset
VLAN
Reserved
Scheduled Send
Insert VLAN
Hardware Parsing
Large Send
TCP/UDP Number
TCP/UDP
Checksum
IP Checksum
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Byte
1Fh:
1Eh
17h
16h
15h:
14h
13h
13h
13h
13h
12h
12h
12h
12h
Bit(s)
15:0
7:0
7:0
15:0
7:5
4
1
0
7
6
5
4
Function
Parameter,
Status
Parameter
Parameter
Parameter
Reserved
Mode
Mode
Mode
Mode
Parameter
Mode
Mode
Description
This field specifies the cumulative number of TCP payload
bytes requested for transmission as part of this IPCB
instance. This field must be valid and will be used when the
Hardware Parsing bit is clear. The Total TCP/UDP Payload
field is ignored when the Large Send bit is clear.
This field defines the offset in bytes from first frame byte
retrieved in memory to the first byte of the TCP or UDP
header. This field is ignored when the Hardware Parsing bit is
set. When the IP Checksum and TCP/UDP Checksum bits
are set and the Hardware Parsing is clear, the TCP Header
Offset parameter must be greater than IP Header Offset
parameter and IP header length combined, as derived from
the data.
This field defines the offset in bytes from first frame byte
retrieved in memory to the first byte of the IP header. The 4
VLAN bytes are not included in the count only if it is inserted
by hardware. This field is ignored when the Hardware Parsing
bit is set.
If the Insert VLAN bit is set, the controller inserts the VLAN
type (8100h, also known as QTAG protocol type). This 16-bit
VLAN ID number and the user priority (32 bits total) are
inserted in the transmitted frame.
These bits are reserved and should be set to 000.
When this bit is set, the controller transmits the associated
frame using the scheduling mechanism.
If this bit is set, the controller inserts the VLAN type and tag
as defined in the VLAN bits description.
When this bit is clear, hardware parsing of the transmitted
packet is disabled. If this bit equals 0 (clear), the IP Header
Offset, TCP Header Offset and total TCP/UDP payload must
be specified to enable checksum operation.
When this bit is set, it indicates that the associated packet
should be transmitted using the Large Send mechanism.
Buffer(s) chained to the IPCB contain data larger than what
may be sent in a single Ethernet frame. The 82550 and
82551 break large packets into smaller ones and transmit
them using several Ethernet frames.
This bit is used to differentiate between TCP and UDP
packets. When it is set, it indicates a TCP frame; when clear,
a UDP frame. This parameter is relevant and required if the
Hardware Parsing bit is clear and the TCP/UDP Checksum is
set.
This bit indicates that the TCP/UDP header checksum should
be performed in hardware.
This bit indicates that the IP header checksum should be
performed in hardware.