RC82562EP Intel, RC82562EP Datasheet - Page 98

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Host Software Interface
90
Table 47. Dump Data Bytes (0-79)
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Configuration parameters and contents of other registers are transferred from the CSMA/CD unit
through the status FIFO by the Command Unit to memory. The CU performs the following
sequence:
Table 47
Link Address
EL (Bit 31)
S (Bit 30)
I (Bit 29)
Bits 28:19
CMD (Bits 18:16)
C (Bit 15)
OK (Bit 13)
Buffer Pointer
0
1
2
3
4
1. Starts the dump action command.
2. Writes the dump command byte to the transit FIFO.
3. Waits for the dump marker to return from the CSMA/CD module.
4. Dumps the FEXT and CSMA/CD registers content through the status FIFO.
5. Dumps the parallel registers.
6. Prepares the status word with C equal to 1 and the OK bit equal to 1.
7. Completes the action command.
Byte
and
FEXT RCV_WR Base Address Register (low)
FEXT RCV_WR Base Address Register (high)
FEXT RCV_WR Current Address Register (low)
FEXT RCV_WR Current Address Register (high)
FEXT RCV_RD Current Address Register (low)
D7
Table 48
This is the 32-bit address of the next command block. It is added to the CU base to
obtain the actual address.
If this bit is set to one, it indicates that this command block is the last one on the CBL.
The CU will go from the active to the idle state after the execution of the CB is finished.
This transition will always cause an interrupt with the CNA/CI bit set in the SCB.
If this bit is set to one, the CU will be suspended after the completion of this CB. A CNA
interrupt will be generated if the device is configured for this. The CU transitions from the
active to the suspended state after the execution of the CB.
If the I bit is set to one, the device generates an interrupt after the execution of the CB is
finished. If I is not set to one, the CX interrupt will not be generated.
These bits are reserved and should all be set to 0.
This is the dump command, which has a value of 110b.
This bit indicates the execution status of the command. Software should reset this bit
before issuing the command to the device. Following a command completion, the device
sets it to one.
NOTE: The difference in the definition of the C bit for the transmit command
The OK bit indicates that the command was executed without error. If it equals one, no
error occurred (command executed OK). If the OK bit is zero and the C bit is set, then an
error occurred.
NOTE: The difference in the definition of the C bit for the transmit command
This field is a 32-bit offset to the dump area address. The size of the dump area is 596
bytes.
describe the dump area format.
D6
(Section
(Section
D5
6.4.2.5).
6.4.2.5).
D4
D3
D2
D1
D0