RC82562EP Intel, RC82562EP Datasheet - Page 59

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.3.6
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 26. Receive Byte Count Register Location
Note: Unless the software uses a very complicated early receive interrupt scheme, which requires the use
Receive Byte Count Register
The early receive interrupt Receive Byte Count (RXBC) register is the 32-bit entity at offset 14h of
the CSR. This read only register reflects the value of the internal receive DMA byte count register.
of header RDFs, this register is of no value to software. Such a scheme could be used by software
to increase performance by decreasing NOS receive latencies. However, most software early
interrupt schemes would increase CPU utilization and software complexity. Thus, use of this
register is not recommended.
Bits 13:11 of this register are reserved and should equal 0. Bits 10:3 contain the receive DMA byte
count. Bits 2:0 are hard wired to 0, giving an 8-byte granularity.
The RXBC register is first initialized to the size of the next receive data buffer. This data buffer
size could equal the HDS size (if header RFDs are used) or the RFD buffer size. When a frame is
received over the wire and passed to memory by the receive DMA, the register decrements until it
reaches zero. At this point the register is set to the size of the next receive data buffer (HDS or
RFD), and the receive DMA is restarted.
2. The LAN controller shifts the following sequence out of the MDIO pin:
3. The PHY shifts the following sequence out of the MDIO pin:
4. The LAN controller discards the leading bit and places the following 16 data bits in the MDI
5. The LAN Controller asserts an interrupt indicating MDI has completed if the Interrupt Enable
6. The LAN controller sets the Ready bit in the MDI register indicating the read is complete.
7. The CPU may read the data from the MDI register and issue a new MDI command.
register.
bit was set.
d. PHYAdd = the PHY address from the MDI register
e. RegAdd = the register address of the specific register to be accessed (0 through 31)
EEPROM Control Register
Upper Word (D31:D16)
<PREAMBLE><01><10><PHYADD><REGADD><Z>
where Z = the LAN controller tri-stating the MDIO pin
<0><DATA><IDLE>
SCB Command Word
Early Receive Interrupt Receive Byte Count Register
SCB General Pointer
MDI Control Register
PORT
Lower Word (D15:D0)
SCB Status Word
Reserved
Host Software Interface
Base + 10h
Base + 14h
Base + Ch
Base + 0h
Base + 4h
Base + 8h
Offset
51