RC82562EP Intel, RC82562EP Datasheet - Page 42

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Host Software Interface
6.3.2.1
34
Table 12. System Control Block
Figure 9. SCB Status Word
Note: TNO interrupts should be avoided. Protocol stacks automatically retry failed transmits. This
Note: The LAN controller latches interrupts internally. Interrupts are PCI compliant and level-triggered.
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
feature should only be enabled if software needs to know immediately about transmit failures.
Interrupt events can only be cleared by CPU acknowledgment. In other words, if the device has
asserted its interrupt pin, the only way to clear it is with a CPU Acknowledgment of that particular
interrupt bit in the SCB. Since multiple events could be active simultaneously, if some events are
not acknowledged by the ACK field, the interrupt signal will remain asserted. However, if a new
event occurs while an interrupt is set, it will not cause an additional interrupt.
The table below shows the SCB format. It is followed by a detailed description on the SCB bits and
their functions.
SCB Status Word
The SCB Status word is addressable as two bytes. The upper byte is called the STAT/ACK byte,
and the lower, the SCB Status byte. The SCB Status byte indicates the status of the CU and RU.
The STAT/ACK byte reports the device status as bits, which represent the causes of interrupts.
Writing to the STAT/ACK bits will acknowledge pending interrupts. As described below, there are
many different possible interrupt events. The LAN controller asserts the interrupt line to the CPU if
any of these interrupt events need to be serviced. More than one STAT/ACK bits may be set at the
same time. Writing 1 back to a STAT/ACK bit that was set will acknowledge that particular
interrupt bit. The device will de-assert its interrupt line only when all pending interrupt STAT bits
are acknowledged. All pending STAT bits do not need to be acknowledged in a single access, but it
is recommended if the interrupt service routine is likely to process all pending interrupts.
Setting a 1 in the interrupt acknowledge command for a non-pending interrupt does not cause any
31
15
STAT / ACK
— A flow control pause frame was received (FCP Interrupt). This does not apply to the
SCB Command Word
82557.
Upper Word
SCB General Pointer
16 15
SCB Status Word
Lower Word
8
7
CUS
0
6
Base + 00h
Base + 04h
Offset
5
RUS
2
0
1
0
0