RC82562EP Intel, RC82562EP Datasheet - Page 63

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.3.10
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 31. Power Management Driver Register
Table 32. General Control Register Location
Note: Not all bits are meaningful in the different generations of devices.
For the 82559, PMDR is initialized at alternate reset only and not at PCI reset (unless a PCI reset
occurs with an alternate reset).
General Control Register
The General Control register provides control over some general purpose features in the 82559. It
is an 8-bit field at offset 1Ch of the CSR. This register is only present in the 82559 and later
generation controllers and is not valid for the 82558 or 82557.
Bits
31
30
29
28
27
26
25
24
EEPROM Control Register
Upper Word (D31:D16)
Operation
Read/
Clear
Read/
Clear
Read/
Clear
Read Only
Read Write
Read Only
Read Only
Read/
Clear
(No clear
on 82559)
SCB Command Word
Default
0
0
0
0
0
0
0
0
SCB General Pointer
MDI Control Register
Description
Valid for 82559 only.
Link Status Change Indication. The link status change bit indicates
change in the link status. Writing a 1 to this bit will clear it.
Valid for 82559 (not 82559ER) only.
Magic Packet. This bit is set when a Magic Packet is received regardless
of the Magic Packet Wake-up disable bit in the configuration command
and the PME enable bit in the PMCSR. Writing a 1 to this bit will clear it.
Valid for 82559 only.
Interesting Packet. This bit is set when an interesting packet is received.
The interesting packet is defined by the 82559 packet filters. Writing a 1 to
this bit will clear it.
Reserved.
Valid for 82558 B-step only.
TCO Ready. When this bit is set (by the driver), the TCO ready signal on
the TCO interface is active signaling the TCO controller that the 82558 is
idle and ready for a TCO cycle.
Valid for 82558 B-step and 82559 only.
Force TCO Indication.
Valid for 82558 B-step and 82559 only.
TCO Request. This bit is set to 1 when the 82559 is busy receiving
packets for or transmitting packets from the TCO controller.
Valid for the 82558 and 82559.
PME Status. This bit is reflects the PME status bit in the PMCSR. It is set
upon a wake-up event, independent of the PME enable bit. Writing a 1 to
this bit clears it. It also clears the PME status bit in the PMCSR and the
PME# signal. Writing a 0 has no effect on the 82558.
PORT
SCB Status Word
Lower Word (D15:D0)
Reserved
Host Software Interface
Base + 10h
Base + Ch
Base + 0h
Base + 4h
Base + 8h
Offset
55