RC82562EP Intel, RC82562EP Datasheet - Page 45

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 14. SCB Command Word Bits Descriptions
When software wants to issue an action command, it should write to the Command byte. The CUC
and RUC fields of the Command byte specify the actions to be performed by the 8255x. The
command is ready for acceptance by the device as soon as it is written into the CUC or RUC field.
The actual command execution may not start instantaneously and will depend on current receive
and transmit DMA activity. The Command byte is set by the CPU and cleared by the 8255x
indicating command acceptance.
Bit
Bits 31:26
Bit 25
Bit 24
Symbol
Specific
Interrupt
Mask Bits
SI
M
Description
The mask bits range from bit 31 to 26. Writing a 1 to a mask bit disables the 8255x
(except the 82557) from generating an interrupt, or asserting the INTA# pin, due to
that corresponding event. The device may still generate interrupts due to other
interrupt events that are not masked. The corresponding bits and their masks are:
These bits are also described in
These bits are not present in the 82557 and should be treated as reserved.
This bit is used for the software generated interrupt. Writing a 1 to this bit causes
the device to generate an interrupt, and writing a 0 has no effect. Reads from this
bit always return a zero. The M bit (bit 24) has higher precedence than the SI bit.
Thus, if a 1 is simultaneously written to both, no interrupts occur.
This bit is used as the interrupt mask bit. When this bit is set to 1, the device does
not assert its INTA# pin (PCI interrupt pin). The M bit has higher precedence than
bits 31 through 26 of this word and the SI bit (bit 25).
31 - CX Mask
30 - FR Mask
29 - CNA Mask
28 - RNR Mask
27 - ER Mask
26 - FCP Mask
Section 6.3.2, “System Control Block
Host Software Interface
(SCB)”.
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