RC82562EP Intel, RC82562EP Datasheet - Page 61

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.3.8
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 28. Flow Control Registers Location
Flow Control Register
The flow control register is a 16-bit field at offset 18h (bits 23:8) of the CSR. This register does not
exits on the 82557. It reflects flow control status information and contains some control bits that
allow software to alter the flow control configuration parameters of the device.
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device is configured to SBF no RFD is reclaimed and the driver may safely assume that an FR
interrupt and RFD status will follow the ER interrupt.
The ER interrupt mechanism operates only if the device does not discard the incoming frames.
Therefore, the device does not generate ER interrupts before the RU is started. The device also
may not assert the ER interrupt for frames that exceed the allocated buffer space and are being
discarded.
When the ER interrupt mechanism is first activated, it may not generate an ER interrupt for the
first frame. An FR interrupt is generated if the RU is ready.
Bits 23:21 - Reserved. These bits are reserved.
Bit 20 - FC Paused Low. This read only bit is an indication of the device flow control state.
It is set by the device when it receives a pause low command with a value greater than zero and
cleared when the flow control timer reaches zero or a pause frame is received.
Bit 19 - FC Paused. This read only bit is an indication of the device flow control state. It is
set by the device when it receives a pause command with a value greater than zero and cleared
when the flow control timer reaches zero.
Bit 18 - FC Full. This read only bit indicates device flow control state. It is set by the device
when it sends a pause command regardless of its cause (either due to the FIFO reaching the
flow control threshold or due to the device fetching an RFD with its FCP bit set or due to
writing into the Xoff bit). The bit is cleared by the device when it exits the above mentioned
state.
Bit 17 - Xoff. Writing 1 to this bit forces the Xoff request to 1. This causes the device to
behave as if the FIFO extender is full. The Xoff request is cleared by writing 1 to the Xon bit
(bit 16). Reading this bit returns 1 after it was set and 0 after the Xon bit was set. This bit
returns 1 after an Xoff request was generated through the RFD Xoff bit until the Xon bit is set.
Bit 16 - Xon. Writing 1 to this bit resets the Xoff request to the device. The Xoff request can
become active through the RFD Xoff bit or if the driver writes 1 to the Xoff bit (bit 17).
Reading this bit returns 0.
Bits 15:11 - Reserved. These bits are reserved.
PMDR
EEPROM Control Register
Upper Word (D31:D16)
SCB Command Word
Early Receive Interrupt Receive Byte Count Register
FC Xon/Xoff
SCB General Pointer
MDI Control Register
PORT
SCB Status Word
FC Threshold
Lower Word (D15:D0)
Reserved
Early Rx Int
Host Software Interface
Base + 10h
Base + 14h
Base + 18h
Base + Ch
Base + 0h
Base + 4h
Base + 8h
Offset
53