RC82562EP Intel, RC82562EP Datasheet - Page 76

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Host Software Interface
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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
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Note:
BYTE 6.
Note:
— Bit 6:0 - Transmit DMA Maximum Byte Count. This byte indicates the maximum number
— Bit 7 - Save Bad Frames.
— Bit 6 - Discard Overrun Receive Frames. This bit determines whether Receive Overrun
— Bit 5 - Extended Statistical Counter.
Default - 0.
Recommended - 0.
of transmit DMA PCI cycles that will be completed after internal arbitration. The counter
has a 4 cycle resolution. It is useful in throttling back the transmit DMA in order to let
other DMA channels, such as the receive DMA, CU DMA, or RU DMA complete PCI
cycles. For instance, if the counter is set to 4, the transmit DMA will only do a 16-cycle
PCI transfer if one of the other internal DMA channels also wants to initiate a transfer. If
no other internal DMA channels are requesting a transfer, the transmit DMA may perform
an extended PCI burst. In order for this counter to be enabled, the DMA maximum byte
count enable bit (byte 5, bit 7) must be set. If the enable bit is not set, the transmit DMA
will continue until it is done (no other DMA unit can pre-empt it).
Default - 0.
Recommended - 0.
This bit determines whether erroneous frames (CRC error, alignment error, etc.) are to be
discarded or saved. Erroneous frames are those where the OK bit equals 0 in the frame
descriptor status field. All frames are saved regardless of their status.
When the device is configured to save bad frames, the Receive Frame Descriptor (RFD) is
not re-used for the next frame. When bad frames are not saved, these structures are re-
used and no information is left in memory.
0 = Received bad frames are not saved in memory.
1 = Received bad frames are saved in memory.
Default - 0 (do not save bad frames).
Recommended - 0 (1 for promiscuous mode).
frames are to be discarded or saved. When activated (set to 0) the device may internally
discard frames that were Overrun. When not activated (set to 1) the device will pass these
frames to memory and only then reclaim the memory space or not according to the SBF
configuration. If this bit is cleared (set to 0), Overrun frames will be discarded regardless
of the setting of SBF. Note that Overrun frames will not always be discarded even if this
bit is activated. If a frame has started to be transferred to memory before the overrun is
detected the frame will be passed to memory regardless of the configuration.
0 = Discard overrun frames.
1 = Pass overrun frames to memory.
Default - 0 (do not pass overrun frames to memory).
Recommended - 0.
This bit is reserved on the 82557, and should be set to 1. For the 82558 or 82559, it
determines the number of statistical counters that are dumped by the device when the
Dump Statistical Counters or Dump and Reset Statistical Counters command is issued. If
If this counter is enabled and set to zero, then the transmit DMA can be pre-empted
almost immediately.
The statistical counters are still updated upon receiving bad frames regardless of
the state of this bit.