RC82562EP Intel, RC82562EP Datasheet - Page 3

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Contents
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2
3
4
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Introduction....................................................................................................................................1
1.1
1.2
Adapter and Controller Overview ................................................................................................ 5
2.1
2.2
2.3
Power Management Interface ....................................................................................................... 9
3.1
3.2
3.3
3.4
PCI Interface................................................................................................................................. 11
4.1
4.2
Scope....................................................................................................................................1
Document Conventions ........................................................................................................2
1.2.1
1.2.2
1.2.3
1.2.4
Adapter Block Diagram ......................................................................................................... 5
Intel Fast Ethernet MAC Features ........................................................................................ 6
2.2.1
2.2.2
2.2.3
Working with the Physical Layer ........................................................................................... 7
Low Power Mode Requirements........................................................................................... 9
Device Power States ............................................................................................................ 9
Power Management Registers ............................................................................................. 9
Link Operation ....................................................................................................................10
PCI Configuration Space .................................................................................................... 11
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10 Built in Self Test (Offset F).....................................................................................15
4.1.11 Subsystem ID (Offset 2C) ...................................................................................... 16
4.1.12 Subsystem Vendor ID (Offset 2E) .........................................................................16
4.1.13 Expansion ROM Base Address Register (Offset 30) .............................................16
4.1.14 The Capabilities Pointer (Offset 34).......................................................................17
4.1.15 Interrupt Line (Offset 3C) ....................................................................................... 17
4.1.16 Interrupt Pin (Offset 3D)......................................................................................... 17
4.1.17 Max_Lat / Min_Gnt (Offset 3E) ..............................................................................18
4.1.18 Power Management PCI Configuration Registers ................................................. 18
PCI Command Usage ......................................................................................................... 21
4.2.1
4.2.2
4.2.3
Device References .................................................................................................. 2
Numbering ............................................................................................................... 2
Signal Name Representation ................................................................................... 2
Memory Alignment Terminology .............................................................................. 2
82557 Features........................................................................................................ 6
82558 Features........................................................................................................ 6
82559, 82550, 82551, and 82562 Features.............................................................7
Vendor ID (Offset 0)............................................................................................... 12
Device ID (Offset 2) ............................................................................................... 12
Command Register (Offset 4) ................................................................................ 12
Status Register (Offset 6) ...................................................................................... 12
Revision (Offset 8) .................................................................................................13
Class Code (Offset 9) ............................................................................................14
Cache Line Size (Offset C) .................................................................................... 14
Latency Timer (Offset D) ....................................................................................... 14
Header Type (Offset E)..........................................................................................14
Memory Write and Invalidate ................................................................................. 22
Read Align ............................................................................................................. 23
Odd Byte Alignment Support ................................................................................. 23
Contents
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