RC82562EP Intel, RC82562EP Datasheet - Page 49

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 16. Statistical Counters
As the above table indicates, the 8255x track of 16 different statistics. However, the 82558 also
maintains three additional statistics (lightly shaded in the above table) for a total of 19 counters. In
addition to the 19 statistics maintained by the 82558, the 82559 tracks two additional statistics and
six reserved statistics (indicated by darker shading in the above table).
The counters are initially set to zero by the device after reset. They cannot be preset to anything
other than zero. The device increments the counters by internally reading them, incrementing them,
and writing them back. This process is invisible to the CPU and PCI bus. In addition, the counters
adhere to the following rules:
Byte Offset
52
56
60
64
68
72
76
78
Applicable to all controllers.
Applicable only to 82558 and later generation controllers.
Applicable only to 82559 and later generation controllers.
Device Statistic
Receive overrun errors. This counter contains the number of frames
known to be lost because the internal receive FIFO overflowed (also known
as receive overrun). This can occur if the device is unable to get the
necessary bandwidth on the PCI (system) bus. If the overflow condition
persists for more than one frame, the frames that follow the first can also be
lost. However, since a lost frame indicator does not exist, these lost frames
may not be counted. A frame that was counted as an overrun will not be
counted in other error counters (short frames, CRC errors, or alignment
errors).
Receive collision detect (CDT) errors. This counter contains the number
of frames that encountered collisions during frame reception. This counter is
always 0 on the 82559.
Receive short frame errors. This counter contains the number of received
frames that are shorter than the minimum frame length. It is mutually
exclusive to the CRC errors and alignment errors counters and has a higher
priority (in other words, a short frame will always increment only the short
frames counter).
Flow control transmit pause. This counter contains the number of flow
control frames transmitted by the device. The count includes both the XOFF
frames transmitted and XON frames (in other words, PAUSE(0))
transmitted.
Flow control receive pause. This counter contains the number of flow
control frames received by the device. It includes both the XOFF frames
received and XON frames (PAUSE(0)) received.
Flow control receive unsupported. This counter contains the number of
MAC frames received by the device that are not flow control pause frames.
These frames are valid MAC frames with the predefined MAC type value
and a valid address; however, they contain an unsupported opcode. In
multimedia mode this counter tracks the pause low frames received. This
count includes both the XOFF_Low frames received and XON_Low frames
(PAUSE_Low(0)) received.
Transmit TCO frames. This counter is incremented when the 82559
transmits a packet initiated by the TCO controller (or ICH device). It should
be noted that any transmission of TCO packets also affects the normal
transmit counters.
Receive TCO frames. This counter is incremented when the 82559
receives a TCO packet. It should be noted that any reception of TCO
packets also affects the normal receive counters.
Host Software Interface
41