RC82562EP Intel, RC82562EP Datasheet - Page 60

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Host Software Interface
6.3.7
52
Table 27. Early Receive Interrupt Register Location
Note: For operating systems with an increased interrupt latencies, the Early Receive Interrupt feature can
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Early Receive Interrupt
be used to mask some of the latency. However, for Linux or Unix operating systems, the Early
Receive Interrupt does not provide any benefit since these operating systems have little interrupt
latencies. Thus, there is essentially no use for this feature in Linux or Unix operating systems.
The Early Receive Interrupt register is an 8-bit field at offset 18h of the CSR. This register is not
present on the 82557. It is used for configuring the device to assert an additional receive interrupt
before the entire packet has been received and deposited into host memory.
When operating with the Early Receive Interrupt scheme, the device generates an early interrupt
depending on the length of the frame. When a frame is received, the controller looks at the Type/
Length field (byte 13 and 14) of the received frame. If the Type/Length field contains a valid length
value (0 < Type/Length
words before the end of the frame. If the Type/Length field contains a Type value, the device does
not generate an early interrupt, except in the case where the Type value is 8137h (IPX) or 0800h
(IP) and the device is configured to generate early interrupts on IPX or IP frames. In these two
cases, it is known that the actual frame length is defined in bytes 17 and 18.
The early receive interrupt value X, in 8 bytes resolution, is programmed into the Early Rx Int
register at address 18h in the device’s CSR. When this value is all zeros no early interrupt is
generated. The Early interrupt is indicated by the ER bit in the SCB. and the assertion of INTA#. X
should be determined by the driver as a function of the interrupt latency, PCI speed, etc.
The device also generates an interrupt at the end of the frame that will assure that no frame is
missed (in case of a race condition), but is in most cases ignored by software (the interrupt is either
already asserted or masked since the driver is in the Interrupt Handler).
The following list describes special cases for early receive interrupt assertion:
•
•
•
If the programmed value is larger than the frame length, the device asserts the interrupt when it
is ready to post the length field into memory.
Short and overrun frames that contain less than the length minus the programmed value do not
generate an early interrupt.
The device does reclaim the RFD used by a frame that caused an early interrupt if this frame is
an error frame and the device is configured to discard bad frames. This implies that the
assertion of an ER interrupt does not guarantee that this frame will also generate an FR
interrupt (in other words, the driver should not poll for the end of frame if it is not set). If the
PMDR
EEPROM Control Register
Upper Word (D31:D16)
SCB Command Word
Early Receive Interrupt Receive Byte Count Register
FC Xon/Xoff
1500), the device generates an early interrupt approximately X quad-
SCB General Pointer
MDI Control Register
PORT
FC Threshold
Lower Word (D15:D0)
SCB Status Word
Reserved
Early Rx Int
Base + 10h
Base + 14h
Base + 18h
Base + 0h
Base + 4h
Base + 8h
Base + Ch
Offset