RC82562EP Intel, RC82562EP Datasheet - Page 50

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Host Software Interface
6.3.3
42
Table 17. Port Register Location
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Software can access the counters by issuing a Dump Statistical Counters SCB command. This
provides a snapshot, in main memory, of the internal statistical counters. For the 82557, this dump
always consists of 16 statistics. For the 82558 and 82559, this dump may contain more statistics
depending on how the device is configured. It is recommended for software to use the following
sequence for maintaining its own statistics:
There should be no interrupts from the device after the completion of this operation. Also, no
changes in the CU status or RU status fields should result after operation completion.
PORT Interface
The Port interface allows software to perform certain control functions on the device. Unlike action
commands, port commands do not require access to the SCB. To initiate a port command, software
should write the appropriate Dword (described below) to the Port register (offset 08h) in the CSR.
Port commands automatically generate an internal selective or complete software reset, depending
on the command. The Dword written as part of a Port command should include:
1. Allocate an array in host memory large enough to hold all of the statistics dumped plus one
2. Load the absolute address of this location into the device using the Load Dump Counters
3. Write zeros to the last Dword in this area. This can be done before or after step 2.
4. Write the Dump Statistical Counters or Dump and Reset Statistical Counters command into the
5. Wait for the device to dump the content of the statistical counters into the allocated memory
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The counters are wrap around counters. After reaching 0FFFFFFFFh, the counters wrap
around to 0. There is no indication when the counters wrap around to 0. Software must track
this.
The device updates the required counters for each frame. It is possible for more than one
counter to be updated as multiple errors can occur in a single frame.
The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The device supports all mandatory and recommended statistics functions through the
status of the receive header and directly through these statistics counters.
additional Dword for status information (for example, 68 bytes for the 82557). This memory
space must be Dword aligned.
Address command.
CUC field in the SCB.
area. The dump is followed by the device writing a completion status into the last Dword in
this area. Software should check this Dword before processing the counters. A value of A005h
indicates the Dump Statistical Counters command has completed. A value of A007h indicates
the Dump and Reset Statistical Counters command has completed.
16-byte aligned address value on the AD31:AD4 data bus pins.
Port function selection code on AD3:AD0
Bits 31:16 (Upper Word)
SCB Command Word
SCB General Pointer
PORT
Bits 15:0 (Lower Word)
SCB Status Word
Base + 0h
Base + 4h
Base + 8h
Offset