RC82562EP Intel, RC82562EP Datasheet - Page 96

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Host Software Interface
6.4.2.6
88
Figure 21. Load Microcode Command Format
Note: Documentation for microcode is beyond the scope of this manual.
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
If neither of these events occurred, the controller generates a CNA interrupt when the CID time
interval has elapsed. The actual delay experienced may be longer than the CID value that was
loaded. The CID is given in a granularity of approximately 256 PCI clocks and the maximum value
is 8192 clocks (which corresponds to 8 to 256 µs in a 33 MHz system).
The delayed CNA interrupt flow is outlined below.
The CNA interrupt delay (CID) field in the TCB is located in bits 28:24 of the first Dword of the
TCB.
Load Microcode (101b)
The load microcode command downloads a 64 Dword microcode patch to the device’s internal
microcode.
The microcode that operates on one device (for example, the 82557), will not operate on another
device (the 82558 or 82559). The load microcode command format is shown below:
00h
04h
08h
260h
1. The delayed CNA interrupt is issued in the suspend or idle state. In other words, if the device
2. The end of receive processing cancels the pending delayed CNA interrupt. It also causes the
3. Resume and start commands cancel pending delayed CNA interrupts. This allows only the last
4. The CX interrupt (caused by the I bit) is not affected in any way by this mode or delay
5. The delay specification is a 5-bit field and ranges between 8 and 256 µs, in 8 µs resolution.
•
Offset
The device received a frame and generated a receive interrupt.
is in the suspend or idle state, raising the interrupt would be delayed by specified time in the
CID field of each command header.
CNA interrupt to be set simultaneously with the frame interrupt, regardless of the internal
counter value. This is based on the theory that any pending transmit cleanup would be done in
the context of a receive interrupt.
TCB of a chain to be interrupted (the rolling delay).
parameter. It may be that regardless of anything else, we may want to interrupt on, say, every
third TX in a chain to return resources to the protocol. This would be accomplished by setting
the I bit in the TxCB. There would be no delay associated with an I-bit interrupt. Note that if I
and S bits are set in a TxCB and the CID field is set to a non-zero value, the CX & CNA
interrupts will not occur together.
The actual delay will only be within a certain percentage of the value specified (but never less
than the specified delay). The inaccuracy percentage is typically in the range of 10 to 20%.
However, in a few extreme conditions (for example, a lot of bad frames received), the delay
may be more than 20% above the specified delay.
EL
Link Address (A31:A0)
First Microcode Dword
64th Microcode Dword
S
Command Word Bits 31:16
I
0000000000
101
C
X
Status Word Bits 15:0
OK
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