HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 109

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Notes: 1. Number of states before the chip enters the sleep state.
Instruction
STC
STC
STC
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STS
STS
STS
STS.L
STS.L
STS.L
TRAPA
2. For details, refer to section 4, Exception Handling.
R5_BANK,Rn
R6_BANK,Rn
R7_BANK,Rn
SR,@–Rn
GBR,@–Rn
VBR,@–Rn
SSR,@–Rn
SPC,@–Rn
R0_BANK,@–
Rn
R1_BANK,@–
Rn
R2_BANK,@–
Rn
R3_BANK,@–
Rn
R4_BANK,@–
Rn
R5_BANK,@–
Rn
R6_BANK,@–
Rn
R7_BANK,@–
Rn
MACH,Rn
MACL,Rn
PR,Rn
MACH,@–Rn
MACL,@–Rn
PR,@–Rn
#imm
Instruction Code
0000nnnn11010010
0000nnnn11100010
0000nnnn11110010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
R5_BANK→Rn
R6_BANK→Rn
R7_BANK→Rn
Rn–4→Rn, SR→(Rn)
Rn–4→Rn, GBR→(Rn)
Rn–4→Rn, VBR→(Rn)
Rn–4→Rn, SSR→(Rn)
Rn–4→Rn, SPC→(Rn)
Rn–4→Rn, R0_BANK→(Rn)
Rn–4→Rn, R1_BANK→(Rn)
Rn–4→Rn, R2_BANK→(Rn)
Rn–4→Rn, R3_BANK→(Rn)
Rn–4→Rn, R4_BANK→(Rn)
Rn–4→Rn, R5_BANK→(Rn)
Rn–4→Rn, R6_BANK→(Rn)
Rn–4→Rn, R7_BANK→(Rn)
MACH→Rn
MACL→Rn
PR→Rn
Rn–4→Rn, MACH→(Rn)
Rn–4→Rn, MACL→(Rn)
Rn–4→Rn, PR→(Rn)
Unconditional trap exception
occurs*
2
Rev. 1.00 Dec. 27, 2005 Page 65 of 932
Privileged
Mode
√
√
√
√
–
√
√
√
√
√
√
√
√
√
√
√
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Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
REJ09B0269-0100
Section 2 CPU
T Bit
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