HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 618

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.12 shows a sample the SCIF initialization flowchart.
Rev. 1.00 Dec. 27, 2005 Page 574 of 932
REJ09B0269-0100
Set transmit or receive format in SCSMR
Read BRK, DR, and ER flags in SCFSR
Set external pins (SCIFnCK, TxD, RxD)
Set TFRST and RFRST bits in SCFCR
TTRG0 bits in SCFCR. Clear TFRST
Clear TE and RE bits in SCSCR to 0
Set CKE1 and CKE0 bits in SCSCR
Set TE and RE bits in SCSCR to 1
Set RTRG1, RTRG0, TTRG1, and
and set RIE, TIE, and REIE bits
and clear the flags by writing 0
(TE, RE, TIE, and RIE bits are
to 1 and clear buffer of FIFO
1-bit interval elapsed?
and RFRST bits to 0.
Set value in SCBRR
Start Initialization
cleared to 0)
End
Yes
Figure 16.12 Sample the SCIF Initialization Flowchart
Wait
No
1.
2.
3.
4.
5.
6.
Keep the TE and RE bits cleared to 0 until initialization
has been completed.
Set the CKE1 and CKE0 bits.
Set the transfer or receive format in SCSMR.
Write a value corresponding to the bit rate in SCBRR.
(Not necessary if an external clock is used.) After this
setting wait for at least 1-bit interval.
Set the external pins. Specifies the pins as RxD input
in reception and TxD output in transmission. Set the
SCIFnCK input/output according to the CKE1 and
CKE0 settings.
Set the TE bit or RE bit in SCSCR to 1. Also, set the
TIE, RIE, and REIE bits. At this time, the TxD, RxD,
and SCIFnCK pins can be used. In transmission, the
TxD pin is in the mark state. When reception in
clock synchronous mode and synchronous clock output
(clock master) are selected, a clock is output from the
SCIFnCK pin.