HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 327

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.3.2
1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register
2. An instruction set for a break before execution breaks when it is confirmed that the instruction
3. When the condition is specified to be occurred after execution, the instruction set with the
4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is
5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the
9.3.3
1. If the L bus is specified as a break condition for data access break, condition comparison is
2. The relationship between the data access cycle address and the comparison condition for each
(BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it
breaks before or after the execution of the instruction can then be selected with the PCBA or
PCBB bit of the break control register (BRCR) for the appropriate channel. If an instruction
fetch cycle is set as a break condition, clear LSB in the break address register (BARA or
BARB) to 0. A break cannot be generated as long as this bit is set to 1.
has been fetched and will be executed. This means this feature cannot be used on instructions
fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to
be executed). When this kind of break is set for the delay slot of a delayed branch instruction,
the break is generated prior to execution of the delayed branch instruction.
break condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When this kind of break is set for a delayed branch instruction and its delay slot, a break is not
generated until the first instruction at the branch destination.
ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle.
instruction fetch cycles on the I bus. For details, see 5 in section 9.3.1, Flow of the User Break
Operation.
performed for the logical addresses (and data) accessed by the executed instructions, and a
break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition
comparison is performed for the physical addresses (and data) of the data access cycles that are
issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is
satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 9.3.1, Flow of
the User Break Operation.
operand size is listed in table 9.3.
Note: If a branch does not occur at a delay condition branch instruction, the subsequent
Break on Instruction Fetch Cycle
Break on Data Access Cycle
instruction is not recognized as a delay slot.
Rev. 1.00 Dec. 27, 2005 Page 283 of 932
Section 9 User Break Controller
REJ09B0269-0100