HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 423

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
12
11
10
9
Bit Name
SLOW
RFSH
RMODE
PDOWN
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Low-Frequency Mode
Specifies the output timing of command, address, and write
data for SDRAM and the latch timing of read data from
SDRAM. Setting this bit makes the hold time for command,
address, write and read data extended for half cycle (output
or read at the falling edge of CKIO). When this bit set to 1,
the hold time for command, address, and write and read
data can be extended. This mode is suitable for SDRAM
with low-frequency clock.
0: Command, address, and write data for SDRAM is output
1: Command, address, and write data for SDRAM is output
Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
Refresh Control
Specifies whether to perform auto-refresh or self-refresh
when the RFSH bit is 1. When the RFSH bit is 1 and this bit
is 1, self-refresh starts immediately. When the RFSH bit is 1
and this bit is 0, auto-refresh starts according to the
contents that are set in RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
Power-Down Mode
Specify whether SDRAM is put in power-down mode or not
after the access to memory other than SDRAM is
completed. This bit, when set to 1, drives the CKE pin low
and places SDRAM in power-down mode by using an
access to a memory other than SDRAM as a trigger.
0: Does not place SDRAM in power-down mode after an
1: Places SDRAM in power-down mode after an access to a
at the rising edge of CKIO. Read data from SDRAM is
latched at the rising edge of CKIO.
at the falling edge of CKIO. Read data from SDRAM is
latched at the falling edge of CKIO.
access to a memory other than SDRAM.
memory other than SDRAM.
Rev. 1.00 Dec. 27, 2005 Page 379 of 932
Section 12 Bus State Controller (BSC)
REJ09B0269-0100